This invention relates to sampling of data at relatively high sampling rates.
A conventional high speed CML data sampler works in two phases: a first phase in which data are tracked, and a second phase in which the tracked data are latched. Ideally, data are sampled in the middle of these two phases. If sampling occurs at a data transition between the two phases, a latch is often unable to resolve a valid output logical state, and an undesirable condition known as metastability occurs. In a conventional approach to reducing or eliminating the occurrence of metastability, a cascade structure of latches is used to reduce, but not to zero, the probability that metastability occurs at a given sampling time. This approach is straightforward, but a small, non-zero probability of metastability remains, depending upon the sampling rate and the length of a transition interval between tracking and latching.
What is needed is an approach that reduces to substantially zero the probability that metastability occurs in data sampling. Preferably, the approach should be flexible and should allow variation of one or more parameters that affect combined tracking and latching.
These needs are met by the invention, which applies a combination of a latching operation and a weak tracking operation that defers to the latching operation when a valid logical state is (already) latched. In one embodiment, additional tracking transistors are connected to latching transistors in the latch module in order to implement weakened tracking. In another embodiment, a driving voltage or current in the tracking module is weakened to suppress competition between a tracking signal and a latching signal and to allow the latching signal to avoid metastability.